On 1/14/2018 9:01 AM, John Heritage via vcf-midatlantic wrote:
The P6 / Pentium Pro did indeed have speculative execution, but branch prediction was used on CPUs far earlier than this. The difference between branch and speculative is that speculative actually fully executes the alternative instruction, where branch prediction simply prepares the core for execution.
IMO - Branch prediction alone shouldn't make a CPU vulnerable to meltdown.
Now fair warning - I'm far from a CPU architect, so if someone has information to the contrary, I'd be very happy to hear the detail.
Thanks, John
On Mon, Jan 8, 2018 at 8:28 AM, David Riley via vcf-midatlantic < vcf-midatlantic@lists.vintagecomputerfederation.org> wrote:
On x86, it's P6 and later, which means back to the Pentium Pro. Not sure when AMD started doing speculative execution; would expect around the K6 or so.
As for other architectures, I would expect the high end ones (SPARC, MIPS, Alpha and PPC) around that time to be included. Really, anything that performs branch prediction (which I know includes all PowerPCs) is by definition engaging in speculative execution, and I'd be quite surprised if any of them that far back were smart enough not to commit the speculatively fetched data to cache or TLBs, which is the main issue here. That's a lot of logic and buffer space on a CPU.
- Dave
IMO - Branch prediction alone shouldn't make a CPU vulnerable to meltdown. I'm no expert either but that makes sense to me too. From what I read its that the speculative execution doesn't apply all the protections that the unspeculative execution does.