So extrapolating to the C64 it could mean: 1. May have been limited due to the specific process fabbing the C64 6502 or support chips and they couldn't communicate higher 2-4 - Not really relevant for the 6502 but may have limited the size of the support chips in the C64 limiting the max frequency they could run at without using dividers. 5. Power distribution - good point, 6502 was pretty low power but more mhz required more beefy power circuits which required more cost; the C64 was an exercise in low cost (although so was the Atari 2600...) 6 - I'd actually to know more about this; Did the 8080 require custom / external solutions to get it to clock higher later on? maybe these were fixed by the Z80. 7-12 these sound like items that could complicate the routing and electronics layouts necessary to make the entire computer work, requiring additional engineering/cost to raise the clock speed of the C64. Am I on the right path for possible (sorry for being less technical) reasons for why the C64 stayed at 1 MHz while it's intended successors (C+, C128) and some contemporaries (A800, BBC Micro) ran at higher clock speeds? Sounds like cost may have been the overall driver.. With the 6502 executing every other clock on many instructions (rating 0.43 MIPs @ 1 MHz), that means RAM needs to at least be double that to allow the custom chips to have their share of every other access, and 4x that if commodore ran the cpu at 2 MHz. On Thu, Mar 23, 2017 at 11:01 AM, Dan Roganti <ragooman@gmail.com> wrote:
On Thu, Mar 23, 2017 at 8:47 AM, John Heritage via vcf-midatlantic < vcf-midatlantic@lists.vintagecomputerfederation.org> wrote:
Does anyone know the reason why the C64 only ran at ~1 MHz? Was it to keep RAM costs or system cost as low as possible or was there a different engineering reason?
(The Atari and BBC machines managed higher clocks, but were very expensive compared to the C= devices, although the 1977 Atari 2600 managed ~1.19 MHz out of it's 6507 (6502 with low pin count/less addressing)..
The various clock circuits inside the different home computers was the least of their problems. All of those different combinations used between the various home computers were just methods they found to minimize their Bill of Materials - because every penny was crucial to their bottom line when making thousands of them in the consumer market.
There were still real and significant design challenges present in the early VLSI designs of the 1970s to make these faster. But they slowly marched on and made improvements every year to where we had the 8086 running at 5mhz and 68000 running at 8mhz already by 1979. This list below is just some of design problems and they are all interrelated. Making trade offs between each of these was a constant battle. This list is mostly ordered by significance, but some of this could be a matter of opinion.
1. BJT, NMOS, PMOS, or CMOS logic families contribute to speed, eg. depletion-load NMOS is faster than BJT 2. Miller Effect [capacitance] prsent even on the silicon die 3. VLSI design geometries were limited to about 5um 4. Clock distribution across the silicon die [eg, too much clock skew] 5. Higher Clock speed required more power dissipation 6. Negative Bias voltage was a burden to compensate for Miller Effect[eg. 8080 ] 7. Lead Inductance present even on the silicon die 8. Slew Rate, eg, ECL being faster ran on smaller voltages, slew rate was less, giving faster clock speed 9. TTL signals are above the noise floor eg, ECL being faster was below noise floor, ie power is negative voltage 10. TTL operate in saturation for logic signals, [eg. ECL being faster operate in Linear region] 11. Square wave logic signals have more odd numbered harmonics than a linear analog device, reducing the possible bandwidth 12. Pin Capacitance limited not only the driver characteristics but also the frequency bandwidth