As promised, I've designed, built, and written up a project for putting a modern static RAM on the OSI bus: http://www.glitchwrks.com/2016/04/23/32k-ram-for-osi Complete with schematics, explanations of the various blocks of the circuit, and assembly tips! This was of course built on one of the clone 495 boards I had made. The linked design is a 32K board based around the common 62256 32K x 8 SRAM, which follows JEDEC pinouts. There's a number of compatible ICs, and you can also use ROM if you like. Memory is split up into 4K segments which can be individually enabled or disabled via DIP switch, allowing you to map around existing memory without disabling it. Pretty simple to build even using point-to-point wiring. I'll be working on adding a second SRAM and expanding the board to 64K this weekend. Another writeup will follow with details on that process. The upper 32K will be switchable like the lower 32K, to allow mapping around I/O devices and optionally enabling that 8K between 0xD000 - 0xE000 that CP/M wants on the 510 CPU board. I designed the circuit so that a Ferroelectric RAM (FeRAM) can be swapped in, with the addition of a write protect circuit. I'll cover that in a later writeup. Is this the sort of thing people would like to see turned into a proper board? I did the schematic in KiCad, so I'd be half the way to creating a board from the prototype. I can do a small run of them and provide either assembled/tested boards or kits. Thanks, Jonathan