Re: [vcf-midatlantic] PDP-8/V project
Cool project! Did you consider using logic closer to DEC's R-series logic, where flip-flops require only two transistors, with a heavy use of diode-capacitor gates and pulse amplifiers? It seems like this would perhaps be a more efficient use of vacuum tubes, as I would suspect a single (dual triode) tube could implement one flip-flop. Thanks, Kyle
Cool project!
Did you consider using logic closer to DEC's R-series logic, where flip-flops require only two transistors, with a heavy use of diode-capacitor gates and pulse amplifiers? It seems like this would perhaps be a more efficient use of vacuum tubes, as I would suspect a single (dual triode) tube could implement one flip-flop.
no, I didn't use any capacitor coupled stuff. That is a good idea though and I have yet to have the boards made for the accumulator, link and program counter so maybe I can experiment with those. Thanks for the good suggestion. Mike
Thanks,
Kyle
Cool project!
Did you consider using logic closer to DEC's R-series logic, where flip-flops require only two transistors, with a heavy use of diode-capacitor gates and pulse amplifiers? It seems like this would perhaps be a more efficient use of vacuum tubes, as I would suspect a single (dual triode) tube could implement one flip-flop.
Looks like it replaces the idiot-proof 6-triode DFF that I was using with a 2-triode SR latch. I could replace my 50% duty cycle clock with a pulse. The pulse has to be wide enough to clock the latch but not too wide so it doesn't get double-clocked. Fortunately there's a long path out of the AC/Link back round to the AC/Link inputs so probably can get away with quite a long pulse in that case. The state machine has some short paths, eg, DEFER2 always and only comes after DEFER1 so there aren't any gates between the two. Worth the research to see what it takes to make it work and not break. Mike
Thanks,
Kyle
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Kyle Owen -
wmrieker＠nii.net