[vcf-midatlantic] Workshop this weekend - Thoughts?
jgevaryahu at gmail.com
Sun Jan 31 22:01:05 EST 2016
I'm trying to extract the actual .jed files from the PLAs for Rev2 and
Rev3, which, if correct, should have the sum16s of 0x7E17 and 0x8411,
As noted in the document, these come from PLAs from Signetics (82S100,
PLS100) and Fairchild (93459).
I'm not as interested in the MOS mask PLA, 906114-01. (either of the two
versions of this, which seem to both behave the same)
To the best of my knowledge, none of the readout/reverse engineering
done by Jens Schoenfield was ever made public. The later decap stuff
was, so we know 100% how the MOS mask 906114-01 PLA worked.
BUT... the reason I'm asking about this is that I don't really trust the
existing prior reverse engineering of the older Signetics and Fairchild
PLAs, since the reverse engineering focus was mostly placed on the
later, MOS mask 906114-01 PLA.
That's why I'm asking about this.
On 1/31/2016 9:29 PM, Rob Clarke wrote:
> Hi Jonathan, take a read of this. The PLA has been exhaustively
> investigated and read using a top max programmer.
> On 31 January 2016 17:24:26 EST, Jonathan Gevaryahu via
> vcf-midatlantic <vcf-midatlantic at lists.vintagecomputerfederation.org>
> Not that I am aware of. The BP-1600 programmer I use uses built-in
> functionality of the PLA to dump the raw original fusemap.
> On 1/31/2016 3:36 PM, Douglas Crawford via vcf-midatlantic wrote:
> Another question related to this:
> If anyone has an older 'breadbox' c64 (not c64c)
> with the signetics 82s100 PLA in it (only used for
> the first year or so before being replaced with
> the MOS PLA) let me know, I'd like to try to read
> the fusemap out with an 82s100 programmer. There
> exists a reverse engineered fusemap of the 82s100,
> but it was done "by hand" using an eprom
> programmer to probe all the inputs and look at
> outputs like a giant truth table, and based on an
> interview with Bil Herd a few years ago, I now
> know that this will not produce an accurate dump
> of the chip, because the engineeres at commodore
> played some tricks by adding extra/unnecessary
> gates to certain outputs to intentionally 'slow
> down' the edges of certain signals to prevent
> Any real risks to the PLA in reading in this fashion?
> Sent from my Android phone with K-9 Mail. Please excuse my brevity.
jgevaryahu at gmail.com
jgevaryahu at hotmail.com
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