What limited the C64's CPU to ~ 1 MHz? , Vol 17, Issue 23

SVCatITC at aol.com SVCatITC at aol.com
Thu Mar 23 20:52:28 EDT 2017

Hi Dan, John;
Newbe here.......
Thanks for the enlightenment on legacy high speed chip design.
Boy does this bring back memories!
Back in the early 80's, had a similar problem designing a quiet  5mHz main 
with dividers, to run test fixture registers, on component hardware from  
production runs.
(Working in the test fixture / model shop.)
In a macro sense, like your 'micro' illustration,  I had harmonic  splash 
all over 
the fixture and DUT circuits..... Way too noisy for testing the low level  
circuits on the hybrid DUT PC board.
I finally ended up taking the main clock components off the main breadboard 
(oscillator and the like), and enclosing them in a total  metal  capacitor 
(forget the alloy) with ceramic feedthroughs for power and clock out.  
With the total metal shield around the 'heartbeat'..... quieted everything  
We all, in the normal thoughts in our brains, think  only digital when we 
are in front of such 
devices, however, when you are designing main 'heartbeats' in these things, 
 you have
to think 'analog' and design around the analog component of the  
rudimentary signals
before moving on to 'clocking' signals and gate chasing around the PC  
In devices that have an analog component (Data Acquisition), have seen  
guard circuit
PC traces totally circling around the 'heartbeat' circuits, for  shielding.
So like the 12 items you identified in rudimentary CPU design, when you are 
that level, one must think basic analog and physics for high speed  design 
and compensate for all the parasitic effects.
As you noted, they all had trade-offs.  It comes down to best bang for  the 
Thank you so much for the refresher course!
Bill Inderrieden

----------- Original Message -------------
Message: 15
Date: Thu, 23 Mar 2017 11:01:04 -0400
From: Dan  Roganti <ragooman at gmail.com>
To: vcf-midatlantic
<vcf-midatlantic at lists.vintagecomputerfederation.org>
Subject: Re:  [vcf-midatlantic] What limited the C64's CPU to ~ 1  MHz?
<CADo=F9Eai8W_OvDosnWSm1vq9tbF+yQHKcB179t5cEBg05HzLA at mail.gmail.com>
Content-Type:  text/plain; charset=UTF-8

On Thu, Mar 23, 2017 at 8:47 AM, John Heritage  via vcf-midatlantic  <
vcf-midatlantic at lists.vintagecomputerfederation.org>  wrote:

>> Does anyone know the reason why the C64 only ran at ~1  MHz?    Was it to
>> keep RAM costs or system cost as low as  possible or was there a 
>> engineering  reason?
>> (The Atari and BBC machines managed higher  clocks, but were very 
>> compared to the C= devices, although  the 1977 Atari 2600 managed ~1.19 
>> out of it's 6507 (6502 with  low pin count/less addressing)..

​> The various clock circuits  inside the different home computers was the
> least of their problems. All  of those different combinations used between
> the various home computers  were just methods they found to minimize their
> Bill of Materials -  because every penny was crucial to their bottom line
> when making  thousands of them in the consumer market.

> There were still real and  significant design challenges present in the
> early VLSI designs of the  1970s to make these faster. But they slowly
> marched on and made  improvements every year to where we had the 8086
> running at 5mhz and  68000 running at 8mhz already by 1979. This list 
> is just some of  design problems and they are all interrelated. Making 
> offs between  each of these was a constant battle. This list is mostly
> ordered by  significance, but some of this could be a matter of opinion.

> 1. BJT,  NMOS, PMOS, or CMOS logic families contribute to  speed,
>      eg. depletion-load NMOS is faster  than BJT
> 2. Miller Effect [capacitance] prsent even on the silicon  die
> 3. VLSI design geometries were limited to about 5um
> 4. Clock  distribution across the silicon die [eg, too much clock skew]
> 5. Higher  Clock speed required more power dissipation
> 6. Negative Bias voltage was  a burden to compensate for Miller Effect
> [eg. 8080 ]
> 7. Lead Inductance present even on the  silicon die
> 8. Slew Rate,
>   eg, ECL being faster ran  on smaller voltages, slew rate was less,
> giving faster clock  speed
> 9. TTL signals are above the noise  floor
>     eg, ECL being faster was below noise  floor, ie power is negative 
> 10. TTL operate in saturation for  logic signals, [eg. ECL being faster
> operate in Linear region]
>  11. Square wave logic signals have more odd numbered  harmonics
>       than a linear analog  device, reducing the possible bandwidth
> 12. Pin Capacitance limited not  only the driver characteristics but also
> the frequency  bandwidth

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